This invention relates to a semiconductor integrated circuit and particularly to a fault detection circuit provided on the same substrate as the main circuit for detecting faults in the main circuit.
For many years industry has employed off chip current monitoring as a means of detecting faults in integrated circuits. This technique is usually employed in conjunction with other traditional test methods such as generating stimulae and observing the output of the circuit and the test. Not only must the fault in question be controlled but also the fault must be observed, making test pattern generation difficult. More recently, pseudo random patterns have been employed with the feature of easy generation. These types of tests can be built into the integrated circuit thus reducing the need for expensive automatic test equipment separate from the circuit. These tests however still miss many defects as they use logic level tests usually based on rather simple fault models.
For example parametric faults such as delay faults and abnormal quiescent current levels are not completely covered by logic fault models. As such, off chip monitoring of the current conducted by the chip improves test coverage. A difficulty however arises due to resolution, that is, if only one transistor on a chip with several tens of thousands is malfunctioning , the defective current has to be resolved from the normal leakage current. In general this process may take an unreasonable amount of time if it is resolvable at all .
It has therefore been a well known requirement for a significant period of time to provide built-in current monitoring directly on the chip since this allows for improved resolution and tailoring of the monitor to various circuit applications such as partitioning I/O and logic blocks with different power requirements or numbers of devices.
Off chip monitoring techniques have therefore been well developed and are widely known and used in practice. The requirement for built-in monitoring is also well known but has up till now found little or no actual implementation.
One example of an arrangement of this type using a built-in testing procedure is shown in U.S. Pat. No. 5,025,344 (Maly et al) issued Jun. 18, 1991. This patent provides a built-in fault detection circuit associated with the main circuit or a part of the main circuit on the substrate and arranged to measure the main circuit current (I.sub.dd). It is well known that the circuit current includes a low quiescent value (I.sub.ddq) while the circuit is not switching which is then significantly increased to a transient value when the circuit is switching in response to stimulation. It is further known that an abnormally high quiescent current is indicative of a fault or faults in the main circuit of a type which may not be detectable using the above mentioned logic level testing. The above patent therefore provides an arrangement which triggers the detection of the circuit current at a time after the transient is expected to have decayed so as to determine whether the quiescent circuit current lies below a predetermined reference current.
The above patent uses a technique which acts to detect abnormally high circuit current from a direct voltage measurement across a non-linear device (BJT transistor). The voltage developed across the BJT transistor is compared to a reference voltage. The voltage is detected between a virtual ground of the main circuit and a global ground of the substrate.
There are several disadvantages of this technique. Firstly, low voltage measurements are susceptible to noise problems and therefore it may be difficult to provide an accurate determination of the value of the current relative to the reference. Secondly, the detection of the voltage between the virtual ground and the global ground requires that the original main CMOS circuit is no longer directly tied to the global ground. The original main CMOS circuit is instead connected only to the virtual ground, which virtual ground is referenced from the global ground by the voltage across the BJT transistor. This technique may therefore have a detrimental effect on the operation of the main circuit, particularly where the output of the main circuit is expected to be transmitted to other portions of the complete integrated circuit.